1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection devices and relevant methods for forming those devices. In particular, the present invention relates to ESD protection devices with islands for constraining ESD current flow and wells thereunder for the prevention of substrate leakage.
2. Description of the Related Art
As products based on integrated circuitry (ICs) become more delicate, they also become more vulnerable to the effects of external environment, especially to ESD stress occurring when one pin of an IC is grounded and anther pin of the IC contacts an electrostatically-precharged object. Therefore, input pins, output pins, input/output pins, the power-bus pins for an IC for communicating with external systems, must all be well equipped with ESD protection devices or circuitry to meet the minimum level of ESD robustness required by commercial applications.
NMOS devices, either with the gate grounded or with the gate coupled to a positive voltage during an ESD event, have commonly been used as primary ESD protection devices for ICs. It is well known that the drain contact of an NMOS device must be kept a few microns apart from the gate of the NMOS device. What is implied is that the drain side of an NMOS device confronting ESD stress in the front line must have a distributed resistor connected in series between the channel under the gate and a coupled pad, and the resistance of the distributed resistor must be larger than an acceptable value. If the ESD transient current starts to localize at a weak spot near the gate, it causes the entire ESD current to rush in, thereby causing local heating and eventually damaging the NMOS device. On the other hand, the distributed resistor helps to raise the potential of the adjacent diffusion area, and hence induce a more uniform ESD current flow towards the whole channel.
The advanced salicide process, which forms silicide material on drain/source regions to reduce the resistance of active regions and speeds up the circuit operation rate, however, makes construction of the above-mentioned resistor more difficult and costly.
One known solution for the problems induced by the salicide process is to use the salicide block process, which blocks the formation of silicide on certain diffusion regions. However, this solution is inefficient due to the process complexity and the extra mask required.
U.S. Pat. No. 5,721,439 (hereafter referred as ""439 patent) discloses an MOS transistor structure comprising a number of isolated islands in the drain diffusion region (as shown in FIG. 1). The ESD transient current flows around these isolated islands from the drain contacts 10, toward the drain-gate edge, thereby increasing drain resistance to improve ESD protection. Due to the manufacture of plasma treatment or carrier ejection in high electric field operations, however, these isolated islands may trap some negative charges inside the isolator material, enhancing recognized gate-induced-drain-leakage (GIDL) current and, therefore, unnecessarily increase standby power consumption.
U.S. Pat. No. 5,248,892 (hereafter referred as ""892 patent) discloses an MOS transistor structure comprising a resistor means whose width is substantially equal to the width of the active zone, wherein the resistor means comprises a number of strips of titanium silicide extending substantially parallel to each to increase drain resistance. U.S. Pat. No. 6,046,087 (hereafter referred as ""087 patent) discloses an ESD protection device using a second gate as silicide-blocking mask for the drain region, wherein the second gate overlies an N-well region and separates the drain of the host transistor into two portions. These two mentioned patents both encounter the problem of the resistor means (""892) or the second gate (""087) contributing resistance rendered un-reducible by the limitation of design rule. In other words, there is a range of resistance unachievable if a drain layout is implemented according to ""892 or ""087 patents.
An object of the present invention is to prevent the occurrence of GIDL current and maintain standby power consumption at a reasonable level.
Another object of the present invention is to provide an ESD protection device that has a distributed resistor with a wider adjustable resistance in its drain side.
Another object of the present invention is to provide a way of re-directing current flow in the drain side of an ESD protection to increase the resistance of the distributed resistor.
The ESD protection device according to the present invention comprises a semiconductor bulk of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the second conductivity type, a channel region, at least one island, and a well of the second conductivity type. The first doped region and the second doped region are formed in the semiconductor bulk. The first doped region further has a boundary. The channel is formed between the first doped region and the second doped region. The island with one end is formed in the first doped region to form a gap between the end and the boundary of the first doped region. The well is formed in the semiconductor bulk, overlaying with the island and being kept at a design distance from the channel region. The well may partially or entirely overlap the island.
In view of the existence of the well, even though the island has trapped charges inside, GIDL current, which flows from a drain side to the substrate under the negative-biased gate, will be limited since at least part of the island overlaps the well. Further, the well also contributes to a lower PN junction capacitance coupling the first doped region and makes the ESD protection device of the present invention more suitable for high speed input/output application.
The wider the gap, the smaller the distributed resistance of the first doped region is. It implies that the distributed resistance of the first doped region can be fine-tuned to a reasonably low level.
Another ESD protection device according to the present invention comprises a semiconductor bulk of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the second conductivity type, a channel region and an array of islands. The first and the second doped regions are formed in the semiconductor bulk. The channel region is formed between the first doped region and the second doped region. The array of islands is distributed at least in the first doped region to force ESD current flowing both backward and forward toward to the channel region. The forward and backward directions are oriented between 90 and 270 degrees of each other.
With the assistance of the islands, ESD current in the first doped region is forced to flow in a serpentine way, forward and backward, toward the channel, such that the distributed resistance of the first doped region is significantly enlarged.
Another aspect of the present invention provides a method of forming an ESD protection device. A well of a second conductivity type is formed in a semiconductor bulk of a first conductivity type. An island overlapping with the well is formed on (or over) the semiconductor bulk. A channel region is formed in the semiconductor bulk and is kept at a designated distance from the well. A first doped region and a second doped region of the second conductivity type are formed adjacent to two sides of the channel region, respectively, wherein the first doped region overlaps the well and the island. The island has one end separated from a boundary of the first doped region to form a gap inside the first doped region.
Another aspect of the present invention provides a method of forming an ESD protection device. A plurality of islands is formed on (or over) a semiconductor bulk of a first conductivity type. A channel region is formed in the semiconductor bulk. A first doped region and a second doped region are formed adjacent to two sides of the channel region, respectively. The first doped region overlaps the islands, which forces ESD current in the first doped region to flow both backward and forward to the channel region.